Quick Specs
Ansys Clock FX automatically identifies and simulates all the clock paths in a design and can account for all critical contributors to clock jitter in each path across multiple processes, voltages, temperature corners and scenarios.
Ansys Clock FX
Variability-Aware SoC Clock Jitter Analysis Software
Ansys Clock FX evaluates all the clock paths in an SoC for clock jitter caused by Supply Noise Variation.
CLOCK JITTER ANALYSIS
Dynamic Voltage Drop and Variation-Aware Clock Jitter Analysis
Ansys Clock FX allows you to calculate clock jitter with variation on a full SoC, without taking any shortcuts. Its unique cell modeling delivers SPICE accuracy timing for any voltage or variation condition with a single library. Clock FX has a fully threaded and distributed architecture, with the ability to scale to thousands of CPUs.
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Add-on to Existing DvD Sign-off Flow
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Native DvD Handoff from Ansys RedHawk-SC
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Clock Mesh Handling
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Simulate Entire Clock
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Clock Jitter Analysis with RedHawk-SC
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Simulate Delays and Clock Jitter on the Clock Paths -
Analyze the Impact of Dynamic Voltage Drop On Clock Jitter -
Create Transistor-level SPICE Models -
Analyze Multi-corner and Multi-scenario Applications
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Perform Non-Gaussian ULV Clock Jitter Analysis -
Simulate Entire Clock Tree -
Obtain SPICE-accurate Jitter Results -
Visualize Full Waveform Propagation
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Take Advantage of Multi-threaded and Distributed Architecture -
Simulate Clock Meshes -
Receive Detailed Jitter Reports Encompassing Various Jitter Types -
Analyze all Advanced Nodes
High-speed and SPICE-accurate clock jitter analysis with voltage, temperature and process variability
Ansys Clock FX is an add-on to existing sign-off flows, with the performance needed to evaluate all clock paths in an SoC for clock jitter on even the largest designs.
Clock FX’s clock path-based timing for delay and jitter can automatically identify and simulate every clock path in your design. It accounts for all critical contributors to clock jitter across multiple processes, voltages, temperature corners and scenarios. Clock FX leverages SPICE transistor models to create a single library characterization that uses full waveform propagation to provide SPICE accuracy and correctly analyze all variability effects with no shortcuts.
Key Features
High-capacity SPICE-level timing using unique voltage, temperature and process-variability-aware cell modeling:
- Accurate clock jitter with dynamic voltage drop
- Single library for all voltages
- Model DvD on VDD and VSS separately
- Comprehensive clock tree coverage
- Add-on to existing DvD signoff flows
- Easily understandable jitter reports
Ansys Clock FX mines the dynamic voltage drop on the clock network produced by RedHawk-SC to calculate clock jitter with SPICE-level accuracy. Clock FX accounts for accurate multi-voltage analysis and simulates the delay impact of supply variation on the clock paths.
Ansys Clock FX automatically identifies and simulates all the clock paths in the design using standard cell models or transistor-level SPICE models. Its full waveform propagation provides the accuracy needed to get reliable results at ultralow voltage and advanced processes.
Ansys Clock FX handles transistor level effects such as voltage drop and ground bounce separately. This enables accurate timing at ultralow voltages where margins are razor thin and variability is severe.
Ansys Clock FX leverages the SPICE transistor models and full waveform propagation to provide the accuracy needed to get reliable results at ultra-low voltage for advanced processes. Miller-capacitance and other effects are handled correctly, with no shortcuts.
Ansys Clock FX is threaded and distributed, dramatically reducing turnaround time and memory requirements, compared to Monte Carlo SPICE.
Ansys Clock FX is tightly integrated with the Ansys sign-off power analysis tool RedHawk-SC to obtain the dynamic voltage drop for simulation. It generates a rich set of jitter reports covering various jitter types.
Ansys software is accessible
It's vital to Ansys that all users, including those with disabilities, can access our products. As such, we endeavor to follow accessibility requirements based on the US Access Board (Section 508), Web Content Accessibility Guidelines (WCAG), and the current format of the Voluntary Product Accessibility Template (VPAT).